ELCT 201 Digital Logic Design Questions

** Problem 1**: Implement a single output circuit that gives an output of logic 1 when the input binary number is equivalent to one of the five decimal digits after the dash in your ID number.

For Example: If your ID number is 49-16382, your output will be equal to 1 if the input binary number in the truth table is equivalent to 1,6,3,8 and 2. I.e.: The output of the function should be logic 1, corresponding to the rows numbered 1, 6, 3, 8 and 2 from the truth table (keep in mind that the first row of the truth table is numbered zero).

For special cases ID numbers; if your ID number is less than 5 digits then embed with zeros to the left most to make them a total of 5 decimal digits. For example, if your ID number is 49-811 (use 49-00811), your output will be equal to 1 if the input binary number in the truth table is equivalent to decimal 0,8 and 1.

The six invalid binary input combinations should lead to don’t care conditions.

The circuit should be implemented using NAND gates only

** Problem 2 **You are required to repeat Problem 1, however this time you should implement the circuit once:

(a) using a decoder **and another time **(b)using a multiplexer.

** Problem 3 **Instead of using numbers that relate to your ID number as in Problem 1, this time you are required to use a form of their complement obtained as follows:

- List the digits of your ID number separately 2. Subtract each digit from 10 3. This new list of subtractions will be the number you have to work with

Example: If your ID number is 49-16382, then the number you will work with is going to be 94728, obtained as follows:

- 10-1 = 9 2. 10-6 = 4 3. 10-3 = 7 4. 10-8 = 2 5. 10-2 = 8

In this problem, you are required to design a counter that moves through the states equivalent to the binary equivalent of the digits of this compliment number. Example: If your ID number is 49-16382; first get it’s compliment number which will be 94728 then find the binary equivalent to each of those digits, as follows:

- 9 is going to be 1001 2. 4 is going to be 0100 3. 7 is going to be 0111 4. 2 is going to be 0010 5. 8 is going to be 1000

These are going to be the states which your counter moves through as follows: 1001 -> 0100 -> 0111 -> 0010 -> 1000 Note the following:

- Upon reaching the end state, the counter should restart again 2. Any unused states should be directed to the initial starting state of your own sequence 3. Your design should utilize D flip-flops

** Problem 4 **In this problem, you are required to redesign Problem 3, but this time utilizing JK flip-flops. Discuss which of both implementations (using D-FF or JK-FFs) has better complexity? ELCT 201 Digital Logic Design Questions